Principles and practices involved in the design, implementation, testing, and evaluation of standard-cell ASIC chips using automated state-of-the-art CAD tools. Topics include hardware description languages, CMOS logic, Finite state machine theory and implementation, and interconnect fundamentals, chip design methodologies, automated cell-based design, CAD algorithms, details of accurately modeling ASIC delay, energy, and area, robustness issues, testing, verification, and debugging, power distribution and clocking, packaging and I/O.